In the last few years, there has seen a shift from continuous-wave systems to pulse-based systems for high-resolution 3D imaging, high-speed wireless communication, and broadband spectroscopy. Designing a receiver to detect sub-100 psec pulses without causing distortion is extremely challenging. This requires a high-performance analog to digital converter (ADC) with an extremely short sampling window. Such samplers primarily exist in expensive III-V materials. Moreover, the ADC architectures have not changed in decades. Every year, the performance of ADCs has been improved by either moving to a newer technology node or by adding circuitry, such as bootstrapping or active cancellation. Such addition comes at a cost of increased area, power, or both. A novel Nonlinear Impulse Sampler architecture is introduced that aims to reduce the sampling window and increase the bandwidth of the system.
Conventional ADCs use Sample and Hold (S/H) or Track and Hold (T/H) architecture to sample the input signal. For example, a series CMOS switches sample the input signal and stores it on a holding capacitor. In these samplers, the series resistance of the CMOS switch (Rswitch) and the size of the holding cap (Chold) determine the time constant of the circuit (τ=Rswitch×Chold) and its effective analog bandwidth. The analog bandwidth of these samplers is limited to 70 GHz. Such architectures are very useful in implementing an ADC with high linearity and resolution. However, these samplers operate at few gigahertz and thus have a relatively large sampling window compared to the proposed architecture. Moreover, to further reduce the sampling window, a high-speed clock with very sharp edges is required. The generation of such a clock with stringent requirement is extremely difficult and consumes large amount of power.
The proposed impulse sampler architecture uses ultra-short impulses to sample the signal. These short pulses activate a nonlinear sampling circuit for only a few picoseconds. One point of novelty of this architecture lies in the on-chip generation of the ultra-short impulse samplers, thus relinquishing the stringent external clock requirements. These improved samplers may significantly reduce the sampling window and increase bandwidth of a system.